module maindec(
    input   logic [5:0] op,
    output  logic       memtoreg,
    output  logic       memwrite,
    output  logic       branch,alusrc,
    output  logic       regdst,regwrite,
    output  logic [1:0] aluop
);

 reg [7:0] controls;

 assign {regwrite, regdst, alusrc, branch, memwrite, memtoreg, aluop} = controls;
 
 always @(*)
    case (op)
        6'b000000: controls <= 8'b11000010;
        6'b100011: controls <= 8'b10100100;
        6'b101011: controls <= 8'b00101000;
        6'b000100: controls <= 8'b00010001;
        default:   controls <= 8'bxxxxxxxx;
    endcase
endmodule